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FPGA & ASIC Design Solutions

ACS Solutions

This is a Contract position in Atlanta, GA posted August 28, 2021.

Job description: RTL coding and simulation in VHDL or Verilog OR Testbench development for the verification of RTL blocks using VHDL or SystemVerilog Digital circuit architecture, design, resource tradeoffs, timing analysis and timing closure Proficiency using ASIC and/or FPGA simulation and synthesis tools (e.g.

Modelsim, Synopsys, FPGA-specific tools) Familiarity with revision control concepts and tools (e.g.

Subversion) Ability to work with minimal supervision, part of a team of engineers with a variety of skills and backgrounds, matrixed into projects with aggressive schedules and frequent milestones.

Strong oral and written communication skills and the ability to document and present one’s work and status Desired skills of a successful candidate: Familiarity with best practice chip-level verification techniques and languages (e.g.

constrained random, functional coverage, SystemVerilog) ASIC / FPGA lab validation with advanced lab equipment Design for Test (DFT) and manufacturability issues Experience with Unix, scripting, C/C++, and/or Perl Job Requirements: Education Bachelor’s Degree in applicable STEM field is required Ability to obtain a US DOD Security Clearance.